Control of impedance of semicon



Oct. 14, 1952 H. L. BARNEY Re 23,563

CONTROL 0F IMPEDANCE 0F SEMICONDUCTOR AMPLIFIER CIRCUITS Original Filed Nov. 6. 1948 6 Sheets-Sheet 1 F/GJ FIG. 2 A FIGS l II/m i sa@ z, 'Q15 4 l Zz 5 6 l? B I NWN/Mr ATTORNEY Oct. 14, 1952 H. L. BARNEY' Re. 23,563

CONTROL OF' IMPEDANCE 0F SEMICONDUCTOR AMPLIFIER CIRCUITS Original Filed Nov. 6. 1948 6 Sheets-Sheet 2 sopoo THANSIS TOR E 0U/ VALE N T C/HCUI T PARAMETERS OHMS 60 l 1 l l n 1 0 .2 I A 6 6 L0 L2 le @annum-Rss) /NVEA/mf? H. L. HARA/EV 37.7 c DAJ ATTORNEV Oct. 14, 1952 H. L. BARNEY CONTROL OF IMPEDANCE OF' SEMICONDUCTOR AMPLIFIER CIRCUITS oiginal Filed Nov. '6, 194e FIG. /5

NPU T' RESISTANCE 6 Sheets-Sheet 3 ik, c, NJ

ATTORNEY Oct. 14, 1952 H. L.. BARNEY CONTROL OF IMPEDANCEAOF SEMICONDUCTOR AMPLIFIER CIRCUITS Original Filed Nov. 6, 1948 6 Sheets-Sheet 4 FIG. 22 s /NVE/vrof? HLBARNEV A TTOFPNE' V Oct. 14, 1952 H. l. BARNEY l Re 23,563

CONTROL OF IMPEDANCE 0F SEMICONDUCTR AMPLIFIER CIRCUITS I Original Filed Nov. 6. 1948 6 Sheets-Sheet 5 )v6.29 F/aao /NVEA/rof? H. L .BARNEY MCM Arron/Ev Oct. 14, 1952 H. L. BARNEY Re. 23,563

CONTROL OF IMPEDANCEOF SEMICONDUCTOR AMPLIFIER CIRCUITS Original Filed Nov. 6. 1948 l6 Sheets-Sheet 6 23 l @i ./RJ y l a* c naar TL?. Y;

ATTORNEY Ressued Oct. 14, 1952 Re. 23,563 l CONTROL OF IMPEDANCE OF SEMICON- DUCTOB AMPLIFIER CIRCUITS Harold L. Barney, Madison, N. J., ssslgnor to Bell Telephone Laboratories, Incorporated,

New

York, N. Y., a corporation ol New York Original Nr. 2,585,977. dated February 12, 1952,

Serial No. 58,684, November 8, 1948. Application for reissue July 3, 1952, Serial No. 297,198

SClaims.

l Matter enclosed-in heavy brackets I liappears in the original patent but forms no part o! this reissue specification; matter printed in italics indicates the additions made 'I'his invention relates to signal translation networks utilizing semiconductor ampliiiers as active elements.

The principal object of the invention is to adjust the impedance oi such a network, viewed at its input terminals or its output terminals, to a desired value.

More particular' objects are: to match the input impedance of such a network to that of a specified source; to match the output impedance of such a network to that of the speciiied load; to make the input impedance of such a network substantially iniinite; to make the input or output impedance of such a network substantially aero; to make the input and output impedances o! suola a network substantially alike in magnitude.

Related objects are to minimize or eliminate interstage coupling deviccsrfrom translating apparatus of s plurality of stages, each of which comprises s semiconductor amplifier network, and to match the impedance of such apparatus as a whole to that of a speciiied source and its output impedance to that of a specified load.

Application Serial No. 11.165 of John Bardeen and W. H Brattain, ilied February 26, 1948 (and after the illing on June 17, 1948, by the same inventors of a continuation-impart application. Serial No. 33,468, now Patent No. 2.524.035, issued October 3, 1950, allowed to become abandoned) describes and claims an ampliiler unit of novel construction comprising a small block of semiconductor material. such as N-type germanium. with which are associated three electrodes. One of these. known as the base electrode, makes low resistance contact with a face of the block It may be a plated metal iilm. The others. termed emitter and collector, respectively. preferably make rectider contact with the block. They may. in fact. be point contacts. The emitter is biased to conduct in the forward direction and the colnectcd between the emitter and the base and e.k

load is connected in the collector circuit, it is found that an amplified replica of the voltage of the signal source appears across the load. The

by reissue.

aforementioned applicationcontains detailed specifications for the fabrication of the device.

'I'he device may take various forms, all'of which have properties which are generally similar although they diier in important secondary respects. Examples of such other forms are described and claimed in an. applicationvof J. N. Shive, Serial No. 44,241, illed August 14,l 194B, and an application of W. E. Kock and R. L. Wallace. Jr., Serial No. 45,023, filed August i9, 1948. and issued July 17, 1951, as Patent 2,560,579. The device in all of its forms has received the appellation transistor, and will be so designated in the present speciiication'.

In the original Bardeen-Brattain application above referred to, there appears a tabulation of the performance characteristics of three smill transistors. In one of these, it appears that increments of signal current which ow in the circuit of the collector electrode as a result of the signal current increments which ilow in the circuit of the emitter electrode exceed the latter in magnitude. This feature oi' transistors has become the general rule, and appears in nearly all transistors fabricated. It is discussed in detail in the aforementioned continuation-in-part application of John Bardeen and W. H. Brattain. Serial No. 33,466. nled June 1'1, 1948, issued October 3, 1950 as Patent 2.524.035. It is ofsuch importance in connection with the present invention, as well as otherwise, that the ratio of these increments has been given a name. s." In one oi its aspects, although not exclusively, the present invention deals with transistors in which s l (s exceeds unit) and is based on the discovery that with a network of which such a device is the active element. the impedance looking into its input or output terminals can, by appropriate proportioning of one of the network parameters in relation to the transistor parameters, be made to take on values which vary over la. much wider range thanis possible with the most nearly analogous vacuum tube' networks It will be explained below, in the detailed description of the yinvention which follows. how it is that the value of a resistor included in the one circuit modiiles the impedance of the other circuit.

The invention will be fully apprehended from the following detailed description of certain prerent:

Figs. 7. 9 and il are graphs showing the variationofthelnputimpedanceoftiienetw'orkof Fig. 3 with load resistance for three representative types of transistor characteristic;

Figs. 8, 10 and 12 are graphs showing the variation of the output impedance of the network of Fig. 3 with source resistance under the same conditions;

Fig. 13 is a schematic circuit diagram of a transistor amplifier network of the vgrounded emitter type; 4

Fig. 14 is the equivalent circuit of Fig. 13;

Figs. 15, 17 and 19 are graphs showing the variation of the input impedance of the network of Fig. 13 with load resistance for three representative types of characteristic;

Figs. 16, 18 and 20 are graphs showing the variations of the output impedance of the network of Fig. 13 with source resistance under the same conditions Fig. 21 is a schematic circuit diagram of a transistor amplifier network of the grounded collector time:

Fig. 22 is the equivalent circuit of Fig. 21;

Figs. 23, 25 and 27 are graphs showing the variation of the input impedance of the network of Fig. 21 with load resistance for three representation types of transistor characteristic;

Figs. 24, 26 and-23 are graphs showing the variation of the output impedance of the network of Fig. 21 with source resistance under the same conditions;

Fig. 29 is a schematic circuit diagram showing a modification of the transistor amplifier network pf Fig. 21;

Pig. 30 is the equivalent circuit diagram of the network of Fig. 29:

Figs. 31, 33 and 35 are schematic diagrams showing further modifications of the transistor amplifier network of I'ig. 21;

Figs. 32. 34 and 36 are the equivalent circuits of the networks of 31. 33 and 35. respecaveu:

Flg.37isaschematiccircuitdiagramof an amplifier comprising a plurality of similar transistor amplifier stages in tandem;

Pig. 38 is a schematic diagram showing a twostage ampliiler oi' which the individual stages are guished by an arrowhead which points inward for N-type material. the collector l by making contact on the same iace of the block as the emitter. and the base electrode l by making contact on the opposite face. The short heavy line l represents the block itself.

Fig. 3 is a schematic circuit diagram of a transistor amplier network in which the transistor itselfisrepresentedbythesymbolofllg. 2. A biassource Ilofperhapsiilvoltsisconnectod to apply negative bias potential to the collector l, while another source Il, usually of a fraction of a volt, is connected to apply a small positive bias potential to the emitter I (or a small negative bias potential to the base electrode l. depending upon one's point of view). A load represented by an impedance Zz. which may be variable, is connected in the collector circuit. A signal source il is connected in the input circuit, l. e., between the emitter 3 and the base I. In addition, an external or "source" impedance Zi is connected in the input circuit. This impedance evidently reduces the signal voltage applied to the input terminals of the transistor. for a given source voltage. but it servesan important purpose as will more fully appear below.

As is now well known. the voltage which appears across the load impedance Z: contains a component which is an ampliiied replica of the source voltage. In addition. it is found that in the great majority of transistors. a is so great that the signal frequency component -of the collector current exceeds the signal frequency component of the emitter current even when the network load impedance Za is of substantial magnitude.

The collector signal current is, corresponding to a given emitter signal current i.. depends on' the collector voltage and on the circuit configura- Therefore a cannot be exactly specified without specifying these matters. A suiiiciently exact definition of a is therefore is more convenient to use.

It is convenient to analyze the performance of transistors for small signalinputs by means of equivalent circuits from which all but the essentials have been eliminated. It has been found that the equivalent circuit which best serves the purposeisaYorTsectionofthreepassivelegs which representthe base impedance, the emitter impedance and-the collector-impedance. respectively, and, in series with the collector leg. a nctitious generator I3 whose electromotive force is proportional to the emitter current. Thus such an eqmvaient cir-cms is shew'n in m. 4. These elements of the equivalent circuit are identiiied herein as emitter. collector and base impedances. but it is to be understood that an actual impedance measurement between two electrodes of the transistor would not necessarily give the simple sum of the respective two impedances. The values of the equivalent circuit elements may be arrived at from such external impedan measurements as follows:

ZesZii-Zu Zarzis where Zii is the impedance measured between the emitter and the base with the collector circuit effectively open; Zn is the impedance measured between the collector and the base with the emitter circuit effectively open:

Zu is the ratio of the signal voltage appearing between the emitter and the base, to the signal current flowing in the collector circuit, when the emitter circuit is eilectively open;-

zsi isthe ratio of the signal voltage appearing between the collector and the base. to the signal current flowing in the emitter circuit when the collector circuit is eectively open.

The assumed directions of current flow ami the polarity o! the electromotive force of the internal generator Il are as shown in Fig. 4 for the above measurements.

Pig. 5 is an equivalent circuit corresponding to the transistor amplier network oi Fig. 3, which is of the "grounded base type; i. c., the base impedance Z is common to both meshes, while the emitter impedance Z and the collector impedance Ze are individual to the first and second meshes. which are identined by mesh currents ii and is in the customary manner. Test voltage sources ei and ez are connected in the first and second meshes for purposes of analysis.

As with Fig. 4, there appears in series with the collector impedance a source of electromotive force =Znie (3) As above stated, the nctitious electromotive force e' which is characteristic of the transistor is found to be substantially proportional to the emitter current i.. The constant of proportionality thus has the dimensions o! impedance, is termed a "mutual" impedance. and is designated Zn.

The foregoing deilnition (2) of n requires that it be determined when the output terminals of the transistor network are short-circuited for si!- nal frequency currents. Furthermore, for the present purposes, the source can ne treated as having no internal resistance. Thus, putting cases and solving the Equations 5 and 6 simultaneously for ii and ii gives :Biz- 51.2. (s)

where A is the determinant of the coemcients of Equations 5 and 8,

but in Fig. 5,

ic=12 ie=1l and therefore Thusbothzmandzcaremanytimesasgreat as Zu; so that, from Equation i0, to a good approximation.

all-

Though the expressions developed hereinafter for input and output impedances are general. the results which follow `will be illustrated with examples involving resistive terminations. and for that part of the frequency scale in which the transistor equivalent circuit parameters are resistive. vThese parameters, when used in this connection, will be referred to as r., re. rc and rin instead of Z.. Z. Zu and Zn, respectively.

Out of the wide range of possible characteristics available among transistors, the results will be illustrated with three diii'erent sets of equivalent circuit parameters. The first. which will arbitrarily be referred to as type l. satisiles the following conditions rsi-500 ohms riaohms r.=20,000 ohms rn==l0`,000 ohms Type 2 characteristics are obtained when the following conditions are met:

a 1 and rili re-1"re-"|!'.. Values of equivalent circuit parameters assumed to illustrate this type are:

re=500 011ml rh=100 ohms te=20,000 ohms n|==40,000 ohms Type 3 characteristics are obtained when a 1 and for. r.l r.+r.+ rb

To illustrate this type. the following values are assumed:

It is to be understood that while all transistorsmaybeclassiiiedaccordingtowhichofthe three foregoing types they coniorm to. their values ot the circuit parameters may vary widely A from the particular combinations assumed above.

Indeed. the parameters tor any one transistor` vary with operating conditions. isillustrated on Fig. 6.. which shows typical' characteristics of r.. n. rs and n plotted against emitter" bias current; i. e., steady current nowingto the emitter electrode (L). At the operating point of 0.5 milliampere emitter current, it will be seen that s which are the values earlier assumed to illustrate the type 2 transistor characteristics. Characteristics for transistors of type 1 and type 3 are similar in their general trends, though particular values of the parameters are numerically diii'erent.

Proceeding now to the investigation of the input impedance of the equivalent circuit oi Fig. 5, and therefore ot the transistor network Fig. 3, put Z1=0 and ea=0 in the foregoing equations 5 and 6 and solve for i1. The result is 1FL-Mizee,

but allowing Z1 and ea to remain ilnite, it turns out that en z dzl-) z"i,`z'+ z..+z.+z.

These more general Equations 14 and 15 may be replaced by the following equations for illustrative purposes:

rb(r.+Ri-r..) Rr'+ r..+r.+R."

assuming` zi and zi to be replaced by R1 and R3. In transistors or wps 1. s 1, so that rm r. and both oi these expressions give positive values for sanos all positive values of R1 and Rs. The variation of Rm and Rm; with Re and R1. respectively. is small. The variations of Rm'and Rm are plotted in Figs. 7 and 8 as functions oi' Rs vand R1. respectively. for the type 1 transistor whose parameters were given above. The input resistance. as shown in Fig. 7, varies between 550 and 600 ohms for a variation of Rs between aero and iniinity and the output resistance, as shown in Fig. 8. varies between 18.400 and 211.100 ohms for a variation ot R1 between aero and innnity.

In transistors of type 2. 1 but r.. r.'+r.+"f i 16) The variations oi Rm and Rim with R1 and Re as shown in Figs. 9 and 10 for a'transistor ot this As shown by the equivalent circuit. Fig. 14. thisr type are somewhat`greater. but'both are still positive for all positive values of R1 and Re.

With th'etype :i"transistorparameters,v where startlingjnew-results are obtained. There'are re- Figs. 11A and 12. which are plots of input as aiunc-tion ot Rsgand oi' output resistancel as 'a lfunction of-Ri. It is apparent that bothy input-resistance and the output resistance .pass- .through zero values, for critical valuesoi Ra R1. respectively,vand are positive for greater values and negative for smaller. Thus, there is furnished a transistor network capable of giving ampliiication. and which has' zero or negative input resistance or zero or negative output resistance. `jli'urtherxnore, these results are independent another. so that they may be obtained separately or together-,as desired. within the limitations imposed by stabilityrequirements. It willhe evident-from inspection of Figs.

ll and 12, thatjthis arrangement is not shortcircuit stableJ-, That is, if both R1 and R.: are zero, the network maybreak into oscillation because o! the negative'resistances oil the input and output circuits. 'It R1=0. Rz must be at least 1550 ohms, or if Riv-:0, R.; must be at least 82.5v

ohms to obtain a stable arrangement.

The critical value 0111:. for which R|s=0, is given by II=rt(1'..,r.)'

Similarly, the output resistance Raue is zero for rfi-r (19) Transistor 4networks oi' the type shown in Fig. 3, in which the input or output resistance has been adiusted in the manner described above to have a zero value, are of use in current measuring instruments. Those in which the resistance has been adjusted to a negative value are of use as negative resistance boosters, and the like. 0n the other hand. and especially when a l. the invention provides a simple and convenient adjustment oi the magnitudes of the input and output impedances of such networks to match positive source and load impedances, respectively.

F18. 13 shows a transistor connected into a network ofv the so-called "grounded emitter type.

term means merely that the emitter impedance Z. is common to the two meshes while the base impedance Z and the collector impedance Zs are individual to the separate meshes. The nctitious 9 electromotive force e' which is characteristic oi' the transistor is again given by Z1+Zb+Z. These may also be rewritten for frequency ranges which are not too high, as

Mrd-R2) Iii-*v+m (20a) and Rout=ru+(re rm)(Rl+rb) where Z1 and Zz are replaced by R1 and R2. These latter expressions are plotted as functions oi' Rz and R1, respectively.

(a) In Figs. 15 and 16 for the illustrative parameter values previously chosen for type 1 transistors, with which 1 and (b) In Figs. 17 and 18 for the illustrative parameter values previously chosen for type 2 transistors with which a f1 and (c) In Figs. 19 and 20 for the illustrative parameter values previously chosen for type 3 transistors with which a 11 and being positive for greater values and negative for lesser values. In addition, and subject to the condition The value of Rm becomes zero when The proximity, along the R2 axis, of the points for which Rinz and Rxnzw makes it a simple matter to vary R2 /between these values in any desired manner, and so adapts the network of l0 Fig. 13, when incorporating a transistor of type 3, to use in modulation systems of the so-called absorption modulation type. Referring to Fig. 18, the output resistance for the network with a type 2 transistor is zero at a value of Ri which, from Equation 21a is given by Tere being positive for lesser values and negative for greater. For a type 3 transistor, for which the output impedance is always negative, but is variable over a wide range of adjustment of R1.

'I'he network of Fig. 13, when adiusted in the manner described above, in addition to providing ampllcation, is useful for matching impedances, as a negative resistance, as a zero impedance device, and in various other connections.

Fig. 21 shows a transistor connected in a network oi' the so-called grounded collector" type. As shown by the equivalent circuit. Fig. 22, this term means merely that the collector impedance Ze is common to the two meshes while the base impedance Zb and the emitter impedance Ze are individual to the separate meshes. The fictitious electromotive force e which characterizes the transistor performance -is again connected in series with Zn and is given by E'Izmie but in this case lez-i2 e1 and ez and source and and Za are connected between and between the output ter- Mesh equation analysis of 20 in the manner outlined Test voltage sources load impedances Z1 the input terminals minals, as before. the circuit of Fig.

Considering the less general case of purely resistive elements. we have on rewriting:

when R1 and Rz are substituted for Z1 and Zz, respectively. These resistances are plotted, as functions of R2 and R1, respectively.

(a) In Figs. 23 and 24 for a transistor of type 1, in which 1 r.. r.+r.+

(b) In Figs. 25 and 26 for a transistor of type 2, in which manner described above, can be put to use 11 (c) In Figs. 2'1 and 28 for a transistor of type 3, in which which is identical with the value o1 Ri for which Rm: reaches zero in Fig. 18. The value of Rn for which Rm has a zero value, in the case of transistors of type 3, is

The network of Fig. 21, when adjusted in the in any of the various connections above referred to in connection with the other ilgures.

It will be observed that in Figs. 19 and 27, those regions are indicated as beingunstable in which the input impedance is positive for values of the load resistance less than that for which it is negative. To understand the nature and explanation o! this instability, consider first the plot oi* the output impedance as a function of source resistance, Fig. 20. This is a negative resistance for any and all values of source resistance be tween aero and infinity. This negative resistance is of the so-called series-type," i. e., the network of which it forms a part will be stable only if a podtive resistance is connected in series with it, of which the value is greater than that of the negative resistance. By way of example, assume that the source resistance Rl is zero. From Fig. 20, the output impedance then appears as a negative resistance of -1550 ohms. If s. load resistance Re equal to or connected to the output terminals of the transistor network, the network as a whole will bel stable. If, however, the value of the external load resistance is less than 1550 ohms, the net resistance in the output circuit will be negative and the network will osciilate or sing. Addition of resistance Ri in the input circuit does not cure the situation but only makes things worse, because, as shown by Fig. 20 any increase of source resistance above zero causes a larger negative value of the output impedance` of the network, which therefore requires a correspondingly larger value of load resistance to prevent oscillation.

Thus, if the external load resistance has a positive value, which is less in magnitude than the negative output resistance for zero input resistance, the system as a whole will be inherently unstable, even though its input impedance appears to be positive, as indicated in those parts of Fig. 19 which lie in the shaded area.

The explanation of instability in the case oi' 27 is the same as numerical values.

greaterl than 1550 ohms is With the networks described above, it is possible to design a single amplifier stage whose input impedance or output impedance is respectively matched to the impedance of a source or of a load as long as these are not too high or too low. A further problem arises when one o: them is innite or zero. Take, for example, the common situation in which it is desired that the input impedance of an amplifier be substantially infinite while its output impedance has a specified value between zero and infinity. This problem may be illustrated in connection with Fig. 2l. The input impedance may be made innite by so choosing R.: that the denominator of (25) vanishes; but it may happen that the load with which the network is to work has a resistance o! widely diiierent value.

This problem is solved, in accordance with the invention in one of its aspects, by the use of an additional variable parameter in the form of a resistor.

It may be readily appreciated that the addition of a resistance in series with emitter, base or collector is equivalent in eil'ect to increasing the magnitude ot r., n or rc respectively, in the foregoing equations for input and output resistance. Fig. 29 illustrates the principle as applied to the 21, and Fig. 30 shows the equivalent circuit. It differs from Fig. 22 b y the addition of the padding resistor Rn in series with the collector. Solution of the network equations in the manner heretofore described but for resistances directly, instead of for the more general impedances yields, for the input resistance:

R=r+r.+r.+R.+R.-.. (29) and for the output resistance:

RDM=TB+MFLLQ (30) It is evident from these equations that the load resistance Rz may be independently chosen, and that it is still possible to make the input impedance infinite by adjusting the sum of Rz and the padding resistor Rp, while using a value of the load resistance Rz which may be dictated by other considerations.

With the network of Fig. 29, a fraction of the power output oi the transistor is absorbed in the i ,padding resistor and is therefore not available that of Fig. 19 except for to the load. Under some circumstances this may be objectionable; and to reduce this power loss without sacrificing the impedance matching advantages of Fig. 29, resort may be had' to still another transistor network which is illustrated in Fig. 3l, while its equivalent circuit is shown in Fig. 32. This network is the same as that of Fig. 2l except for the addition of a feedback resistor Rr in shunt with the input terminals of the transister. This addition results in the addition of a third mesh to the network. designated i: in Fig. 32. Solution of the'mesh equation yields, for the input resistan:

product by the sum of Equation 25a and Rr. In

other words. Equation 31a is the mathematical statement of thmfact that in Figs. 31' and 32 the grounded collector network of Fig.

this'V input resistance of the network of Fig. 29 as given by Equation 25a has been reduced by connecting the resistor Rr in shunt with the input terminals of Fig. 29 and for the output resistance:

From Equation 31 it is evident that, within the restriction the input impedance may take on values which are positive, negative, zero, or infinite, as required, in dependence on the values of R2 and RF. This evidently gives greater freedom in the selection of the load resistance, as compared with Equation 25 which applies to the network of Fig. 21, in the same manner that the use of the padding resistor in Fig. 29 provides such freedom. At the same time, all of the power output of the transistor is furnished to the load, at the expense of some power absorbed in RF. The latter power is driven from the source rather than from tran- Asistor. This difference is of advantage under some circumstances.

In the vacuum tube amplifier art, it is known that certain advantages accrue from the use of negative or inverse feedback. The conventional cathode follower vacuum tube circuit with large, unbypassed cathode resistor embodies the inverse feedback principle, and, as is well known, the input impedance of such a circuit, looking into its grid and load resistor terminals is greatly increased, as compared with that of a grounded cathode circuit employing the same tube. The networks oi' Figs. 21, 29 and 31 may be looked upon as embodying the same negative feedback principle but they differ from the most nearly analogous vacuum tube circuits in that the input impedance may take on the widely varying values discussed above. 'I'he effect of the resistor Rr in Fig` 31 may be looked upon as further increasing the inverse feedback of Fig. 21 by providing a second path, in addition to that through the source resistance R1, through which the feedback current can flow, and so furnishing a greater current to the base electrode for a given voltage` drop across the load resistor, or a greater voltage feedback for a given emitter current, depending on one's point of view. The mode of operation of the network of Fig. 31 can also be looked upon as follows: Elimination of the padding resistor Rp of Fig. 29 effectively reduces the total resistance in the output circuit of the transistor below the value at which the input impedance becomes infinite. As a result, the input impedance of the transistor, without theI feedback resistor RF, is negative. Insertion of the feedback resistor Rrof the proper magnitude now places a positive resistance inv shunt with the negative input resistance of the transistor network of just such a magnitude as to bring the input impedance of the network as a whole back to infinity.

Still further flexibility results when the padding resistor Rp of Fig. 29 and the feedback resistor Rr o1' Fig. 31 are embodied in the same transistor network. Such a network is shown in Fig. 33 and its equivalent circuit is shown in Fig.

34. The expressions for the input and output impedances are like those for Fig. 31 but for the 14 fact that the collector resistance rc is to be replaced, wherever it occurs, by

Icf-Rp and that the condition 32 i' is repmced by Im (R2+I`e+1c-|Rp) (33) Instead of merely increasing the inverse feedback due to R2 by the use of a shunting resistor as in Fig. 33, an additional negative feedback current may be drawn from the collector and fed to the base electrode by way of a feedback resistor Rr', as in Fig. 35. Here Cl and Cz are merely blocking condensers of negligible impedance at signal frequencies and are omitted from the equivalent circuit Fig. 36. 'I'he resistor RF' therefore carries a current to the base electrode, which current is in phase with the collector voltage. In the absence of the feedback path, there is a phase reversal between the voltage on the base electrode and the voltage on the collector. Therefore the feedback furnished by way of the resistor Rp' is negative or degenerative, and its use carries with it all of the advantages which are now well known in connection with negative feedback such as the stabilization of amplifier gain, reduction of noise, etc. Solution of the mesh equations of Fig. 36 shows that the input impedance becomes infinite subject to the same condition (33) and for slightly different values of Rz, RF and Rp. 'I'he differences, though slight from the analytical standpoint, may become critical in particular circumstances.

'I'he various networks of the invention may be coupled together in various ways. Fig. 37 shows a three-stage amplifier coupling an incoming line 20 to an outgoing line 2|. Characteristic impedances of these lines may be alike. 'I'he operation of tandem stages without using interstage transformers presents a problem to the designer of transistor networks who has not the benefit of the present invention. The input resistance of the first stage may be matched to the resistance of the source, that is of the incoming line 20, by use of the appropriate transformation ratio in an input transformer 22. In each stage the resistances R3 and R4 may be assumed to be very high resistances so that thesr do not appreciably shunt the output of the stage ahead of it or the input of the following stage. The load on the first stage is therefore the series combination of an interstage resistor Rs and the input impedance of the second stage. Since Rs appears both in the input impedance and the output impedance, it may be adjusted to serve both purposes.

The application of the foregoing principles to this particular problem is illustrated for a typical transistor of type 2, in which rb= ohms r=500 ohms rc=20.000 ohms rm=40,000 ohms 'I'he output load on the first stage is the sum of Rs and the input impedance of the following stage. Equation 20a is a general expression for the input resistance of a grounded emitter transistor amplifier stage as a function of its load resistance. In this expression, replacing Rz by Rs-i-Rln gives 15 Insertion of the numerical values listed above in this expression gives ohms terminals. to its input termination, i. e., R1=Rm, gives (r.rm)(Rf..-|rb) Rm r+ Rin+rb+rn Inserting the foregoing numerical values, with Rm still undetermined, gives The conditions of the problem are that the input terminating resistance of each stage shall be equal to the series combination of Rs with the output impedance of the prior stage, or

Rin=RB+Rout Simultaneous solution of these three equations gives, for the assumed numerical values:

Rin-:4,500 ohms Raum- 15,600 ohms :20,100 ohms Since the stages are all to be alike, this result holds for any stage, so that a multistage ampliiler of as many stages as may be desired can be built up, in which each input impedance is 4,500 ohms, and in which, furthermore, the effective output impedance of each stage (Raum-Rs) is likewise 4,500 ohms. Transformers 22, 2l, or other impedance matching networks may now be connected at the input and output terminals of the' amplifier as a whole to eifect a match to the incoming and outgoing lines 20, Il. Each stage of the amplier, using the assumed numerical values, has a power gain of 18 decibels, which would be impossible to secure in a multistage ampliier in which interstage impedance matching was obtained merely by the use of padding resistors in series with the input circuits and potentiometers in the output circuits.

It will be noted that, in Fig. 37, the emitter bias battery il of the earlier figures has been omitted. It is replaced, in the first stage, by a self-bias circuit of the type which forms the subject-matter of an application of R. C. Mathes and H. L. Barney. Serial No. 22,854, led April 23, 1948 and issued August 8. 1950, as Patent 2,517,960 and in the second and third stages by a different selfbias arrangement, which forms the subject-matter of an application of H. L. Barney, Serial No. 123,507, filed October 25, 1949. The shunt resis R4 are required to be of fairly low value from the standpoint of self-bias alone while. in order to reduce their shunting eifect across the input terminals of the amplifier stage, they are required to be of high value. These incompatible requirements can be resolved by the addition of a resistor-condenser combination R1, C1 connected between the emitter electrode and ground. 'Ihe resistor R1 is by-passed for signal frequency purposes by the condenser C1 but it carries a potcntiall drop which is nearly equal in magnitude to that across the shunt resistor Re. By this means self-bias of the base electrode with respect to the emitter-.inthe required magnitude of a fraction of a volt is secured for the transistors of placed on the ampliner of Fig. 37 may be considered too severe. For most purposes a sumcient requirement is that (a) the input impedance of the first stage of an amplifier match the source impedance; (b) the output impedance of each stage match the input impedance of the following stage; and (c) the output impedance of the' last stage match the impedance of the load. Requirements of this type may be met comparatively simply in a two-stage amplifier network with a. circuit such as that of Fig. 38. in which transistors having type 1 characteristics are used. Here, assuming the values of resistors Rs and Re, which merely supply operating potentials to the electrodes, to be high, the load on the first or grounded-emitter stage consists merely of the input impedance of the second stage. Thus condition (a) may be met by selecting the first stage output termination in accordance with Equation 20a; condition (b) is met by selecting the second stage output termination in accordance with Equation 25a at such a value that its input impedance is equal to the output impedance of the first stage as just determined, and, lastly, condition (c) is met by constructing the resulting outputtermination of two parts, the load itself and an adjustment resistor Rs'. The latter is shown with the load. Circumstances may require that it be connected in series with the load instead.

Fig. 39 shows a two-stage amplider of which the ilrst stage is of the grounded base type (Fig. 3), while the second stage is of the grounded collector type with padding resistor Rp (Fig. 29). Transistors having type 1, 2 or 3 characteristics may be used in either stage of this amplifier. The resistors Rs, Re and Rs of which Rs and Rs are self-bias resistors, merely serve to apply correct operating potentials to the electrodes. With the compensating resistors R1 and R1 in the circuit, Rs and Rs may be of such large value as not seriously to shunt the source or the tlrst stageoutput. By reason of the direct interstage coupling (Ci and C: are merely blocking condensers) the output terminating limpedance seen by the first stage is the input impedance oi' the second. In the manner explained above, but using the impedance expressions appropriate to the networks, namely, Equations 14 and 15 for the first stage and 29 and 30 for the second. and finally selecting the adjustment resistor R1' so that when it is connected in parallel with the load as shown. or in series with the load, this combination of resistor R1' and the load presents the necessary impedance to the output terminals of the second stage.

In place of the padding resistor R0 of Fig. 39. the feedback resistor Rr of Figs. 33 and 35 may be employed, if desired, to give flexibility to the choices of the other resistors. Fig. 40 shows a two-stage ampliiier in which the second stage is like Fig. 31. and Fig. 41 shows one in which the second stage is like that of Fig. 35. The impedance matching principles. and the manner in which they are to be put in practice. are as explained above, due regard being had to the expressions governing the input and output impedances of the transistor network employed in each case.

Reference is made to two divisions of the present application, both of which were filed on November 15, 1949, namely. application Serial No. 127,439, now Patent 2,550,518, issued April 24,

u 17 1951, and application Serial No. 127,440, now Patent 2,541,322, issued February 13, 1951. Reference is also made to a related original application Serial No. 58,685, iiled November 6, 1948, now Patent 2,585,078, issued February 12, 1952.

What is claimed is:

1. An amplifier network having an adjustable input impedance which comprises a transistor comprising a semiconductive body. a base electrode, an emitter electrode and a collector electrode cooperatively associated therewith, said transistor being characterized by a ratio of shortcircuit collector current increments to emitter current increments which, under proper conditions of electrode bias is greater than unity, means including an energy source for establishing said proper bias conditions. an input circuit interconnecting said base electrode and said emitter electrode, an output circuit interconnecting said emitter electrode and said collector electrode, and a load connected in said output circuit, the eiective resistance R.: oi' said load being proportioned in accordance with the formula where r=`emitter resistance oi' the transistor rxrbase resistance of the transistor rczcollector resistance of the transistor rmzzmutual resistance of the transistor Rxnzinput resistance of the transistor network tions of electrode bias is greater than unity,l

means including an energy source for establishing said proper bias conditions, an input circuit interconnecting said base electrode and said emitter electrode, an output circuit interconnecting said emitter electrode and said collector electrode, and an input termination connected in said input circuit. the eilective resistance R1 of said termination being proportioned in accordance with the formula where rezemitter resistance of the transistor rar-base resistance oi' the transistor r=co1lector resistance o! the transistor rmzmutual resistance of the transistor Rwrzoutput resistance of the transistor network to cause the output impedance of the network to have a desired value.

[3. An amplifier network having a substantially zero input impedance which comprises a transistor comprising a semiconductive body, a

i base electrode, an emitter electrode and a collector electrode cooperatively associated therewith. said transistor being characterized by a ratio of short-circuit collector current increments to emitter current increments which, under proper conditions of electrode bias is greater than unity, means including an energy source for establishing said proper bias conditions, an input circuit interconnecting said base ,electrode and said emitter electrode. an output where r=emitter resistance of the transistor :base resistance of the transistor r=collector resistance of the transistor rm=mutual resistance of the transistor] [4. An amplier having a substantially zero output impedance which comprises a transistor comprising a semiconductive body. a base electrode, an emitter electrode and a collector electrode cooperatively associated therewith, said transistor being characterized by a ratio o1' shortcircuit collector current increments to emitter current increments which. under conditions of electrode bias is greater than unity. means including an energy source for establishing said proper bias conditions, an output circuit interconnecting said emitter electrode with said collector electrode, an input circuit interconnecting one of said last-named electrodes with said base electrode, and a terminating resistor Rrconnected in said input circuit. said resistor having a value substantially by the formula where rezemitter resistance of the transistor rn=base resistance o1' the transistor rs=collector resistance oi the transistor rm=mutual resistance of the transistor] [5. An amplifier having a substantially infinite 4input impedance which comprises a transistor comprising a semiconductive body, a base electrode, an emitter electrode and a collector electrode cooperatively associated therewith, said transistor being characterized by a ratio o1' shortcircuit collector current increments to emitter current increments which, under proper conditions oi' electrode bias is greater than unity, means including an energy source for establishing said proper bias conditions, an output circuit interconnecting said emitter electrode and said collector electrode, an input circuit interconnecting one oi' said last-named electrodes with said base electrode, and a load resistor Rz connected in said output circuit, said resistor having a value given substantially by the formula RIZI'ln-le-Ic where rezemitter resistance of the transistor rs=base resistance of the transistor rczcollector resistance o1' the transistor rmzmutual resistance of the transistor.)

6. An amplifier adapted to be connected in cascade between a low impedance source and a low impedance load, which comprises a iirst transistor amplier network ot the grounded emitter configuration, having output terminals, an intrinsically low input impedance and an intrinsically high output impedance, a second transistor ampliiier network of the grounded collector connguration having input terminals connected to the cases output terminals of the first network. an output circuit, a resistor. said resistor and said low impedance load being connected in said ouput circuit, said resistor being proportioned. in dependence on the impedance of said load, to make the input impedance of the grounded collector stage equal to the output impedance of the groundedemitter stage. I

7. A multistage ampliiier comprising a plurality of like transistor amplifier networks coupled together in cascade, each of said networks having input terminals and output terminals, a plurality of resistors. each connected in series between the output terminals of the preceding network and the input terminals of the following network, and each having a resistance value Rs which satises the relations 8f An ampliiler of two stages adapted to be connected between a low impedance source and a low impedance load, the first stage comprising a transistor amplifier network of the groundedemitter configuration having input terminals, output termina1s.an intrinsically low but controllable input impedance and an intrinsically 20 high but controllable output impedance. the second stage comprising a transistor network of the grounded-collector configuration having input terminals, output terminals. an intrinsically high but controllable input impedance and an intrinsically low but controllable output impedance. the input terminals of the second stage being directly connected. for signal frequencies, to the output terminals of the first stage. the input impedance of the second stage thus constituting the output termination of the ilrst stage, a resistor, said resistor and said load being connected to the output terminals of the second stage. said resistor and said load. taken together. being so proportioned in relation to the transistor parameters as to make the input impedance of the second stage, and thus the output termination of the ilrst stage, match the output impedance of the rst stage and of such a value as to make the input impedance ot the nrst stage matchv the impedance oi' the source. said resistor being so proportioned in relation to said load as tomake-said resistor and load, taken together, match the output impedance of the second stage.

HAROLD L. BARNEY.

REFERENCES CITED The following references are oi' record in the file of this patent:

UNITED STATES PATENTS Number Name Date 1,778,085 Nyquist Oct. 14, 1930 1,877,140 Lilienfeld Sept. 13, 1932 1,949,383 Weber Feb. 27, 1934 2,476,323. Rack July 19, 1949 2,517,960 Barney et al. Aug. 8, 1950 

